library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signextend is
	generic
	(
		IMM_WIDTH	: natural  :=	16;
		DATA_WIDTH	: natural  :=	32
	);


	port
	(
		-- Input ports
		immediate	: in  std_logic_vector(IMM_WIDTH-1 downto 0);
		se	: in  std_logic;
		
		-- Output ports
		extendimm	: out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end signextend;

architecture rtl_signextend of signextend is

begin
	process (immediate)
	begin
		if se = '1' then
			extendimm(IMM_WIDTH-1 downto 0) <= immediate;
			if immediate(IMM_WIDTH-1) = '1' THEN
				extendimm(DATA_WIDTH-1 downto IMM_WIDTH) <= X"FFFF";
			else
				extendimm(DATA_WIDTH-1 downto IMM_WIDTH) <= X"0000";
			end if;
		else
			extendimm(IMM_WIDTH-1 downto 0) <= immediate;
			extendimm(DATA_WIDTH-1 downto IMM_WIDTH) <= X"0000";
		end if;
	end process;
end rtl_signextend;
